Chip scale package structure for an image sensor
US7173231B2 · kind B2 · utility
5Cited by
5References
8Claims
0Family size
Inventor
Key dates
| Filing date | Sep 16, 2003 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | May 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A chip scale package (CSP) structure for an image sensor includes a semi-conductor image sense chip and multiple bonding pads formed on a top face of the semi-conductor image sense chip. A conducting wire extends from each of the multiple bonding pads by wire-bonding. Liquefied jelly-like material is covered with the top face of the semi-conductor image sense chip and forming a transparent layer on the top face of the semi-conductor image sense chip after drying up. The transparent layer has a thickness being equal to a height of each of the conduct wire relative to the top face of the semi-conductor image sense chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.