Sampling phase detector for delay-locked loop
US7173460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2005 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | May 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay-locked loop (DLL) architecture is provided that includes a voltage controlled delay line, a sample-and-hold circuit and an amplifier circuit. The voltage controlled delay line may have a plurality of buffer stages to provide a first clock signal and a second clock signal. The sample-and-hold circuit may receive signals corresponding to the first clock signal and the second clock signal. The sample-and-hold circuit may provide two sampled signals based on the received signals. Additionally, the amplifier circuit may be coupled to the sample-and-hold circuit and the voltage controlled delay line. The amplifier circuit may provide a control voltage to the buffer stages of the voltage controlled delay line based on the sampled signals received from the sample-and-hold circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.