Clock sources and methods with reduced clock jitter
US7173470B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2005 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | May 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock sources are provided which are especially useful for reducing phase noise in signal samplers that typically provide samples of an analog input signal in signal-conditioning systems such as analog-to-digital converters. This phase noise reduction is realized with the recognition that sampler noise is related to clock jitter by a ratio of the input signal's slew rate to the clock's slew rate. Clock embodiments include a frequency divider and a signal gate. The divider divides a first signal to provide a second signal with a slew rate lowered from the slew rate of the first signal and the gate passes the second signal when commanded by the first signal to thereby generate a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.