Trailing artifact avoidance system and method
US7173971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2002 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Jan 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/521
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method is provided to avoid or otherwise reduce luminance and/or chrominance trailing artifacts in block-based hybrid video coders using multiple block sizes and shapes. The proposed trailing artifact avoidance approach has at its core three main components. The first component is a method to identify flat blocks in the source frame that are most susceptible to the appearance of trailing artifacts, and where flatness is determined according to several proposed criteria. The second component is a method to identify bad blocks, which refer to predicted blocks in motion estimation that correspond to flat blocks in the source frame and that contain trailing artifacts. The third component is a method to avoid trailing artifacts when they are detected within a bad block, and where the avoidance is achieved by employing one or more tools from among a proposed set of high fidelity coding tools and/or high performance motion estimation tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.