Method and system for performing permutations with bit permutation instructions
US7174014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2001 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Oct 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of instructions with each sequence specifying the position in the source for each bit in the destination. In the PPERM instruction bits in the destination register that change are updated and bits in the destination register that do not change are set to zero. In the PPERM3R instruction bits in the destination register that change are updated and bits in the destination register that do not change are copied from intermediate result of previous PPERM3R instructions. Both PPERM and PPERM3R instructions can individually do permutation with bit repetition. Both PPERM and PPERM3R instructions can individually do permutation of bits stored in more than one register. In an alternate embodiment, a GRP instruction is defined to perform permutations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.