Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host
US7174411B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Apr 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. The host has 2N primary lanes plus one extra lane. The extra lane is allocated to a slot when another slot uses all 2N primary lanes. The extra lane ensures that a low-priority peripheral has at least one lane when a high-priority peripheral requires all primary lanes. A partial cross-bar switching matrix between the host and peripheral slots switches lanes at the physical layer using transistor bus switches. A switch controller can be programmed by configuration software to enable transistor bus switches to allocate and connect host lanes to slot lanes. Peripherals can have 1, 2, 4, 8, 12, or 16 lanes allocated and may be inserted into any of the slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.