Test system rider utilized for automated at-speed testing of high serial pin count multiple gigabit per second devices
US7174490B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Aug 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31903
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing system performs simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates coupled to a DIB and device connectors on the DIB. The testing system includes a rider board including rider board connectors coupled to corresponding ones of the device connectors, an individual set of multiplexers coupled to each one of said rider board connectors, a controller coupled to each of said set of multiplexers, and an internal testing system including a tester and testing system multiplexers, said tester being coupled to each of said set of multiplexers via said testing system multiplexers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.