Fabrication of nanoelectronic circuits
US7176066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | May 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/3835
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.