Manufacturing method of thin film transistor array substrate
US7176074B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2006 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Aug 10, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of thin film transistor array substrate is provided. A substrate, whereon first, second, and third poly-silicon islands, a gate insulating layer, a plurality of first, second, and third gates, and a first passivation layer have been formed, is provided. A third patterned photoresist layer is formed on the first passivation layer by using a third half-tone mask. A first ion implantation process is performed with the third patterned photoresist layer as mask to form first sources/drains. A portion of the thickness of the third patterned photoresist layer is removed, and then portions of the first passivation layer and the gate insulating layer are removed with the third patterned photoresist layer as mask to form the first patterned passivation layer. The third patterned photoresist layer is removed. First, second and third source/drain conductive layers, a second patterned passivation layer, and pixel electrodes are formed in sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.