High-speed, current driven latch
US7176736B2 · kind B2 · utility
1Cited by
12References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 20, 2004 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Jan 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/288
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.