Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs
US7176737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Jun 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.