High bandwidth datapath load and test of multi-level memory cells
US7177186B2 · kind B2 · utility
1Cited by
2References
6Claims
0Family size
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Key dates
| Filing date | Mar 28, 2006 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Mar 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.