Buffer management for merging packets of virtual circuits
US7177279B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2002 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5682
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus for coordinating merging of packets for one or more virtual circuits (VGs). Each packet of a VC comprising a sequence of cells terminates with an end of packet (EOP) cell. The apparatus comprises one or more buffers, a buffer controller, and a merge processor. Each buffer is configured to receive cells of an associated VC and a threshold value based on traffic of the VC. When a number of cells of a packet in a buffer exceeds the corresponding dynamic threshold value, a corresponding flag of the buffer is set. The buffer controller is configured to drop all cells of the current packet in response to a set flag of a corresponding buffer. The merge processor services each buffer in accordance with a scheduling method to transfer one or more packets from each buffer to an output packet stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.