Data transfer processing apparatus, data transfer method, and data transfer program
US7177280B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 23, 2002 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Apr 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/30
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This invention is intended to realize with ease flow control and quantization error reduction in a data transfer operation executed via the IEEE 1394 serial bus. A FIFO once holds data supplied from a decoder and outputs the data in a predetermined send timing relation. At this moment, a counter counts the number of packets to sent from the FIFO to an IEEE 1394 bus. In order to increasing data transfer quantity in accordance with a send command issued by a register, a data packet is sent at transfer of an empty packet. In order to decrease data transfer quantity, an empty packet is sent in a timed relation in which a data packet is sent. A data quantity monitor requests the decoder for supplying data or stopping thereof via a data input controller so as to prevent the FIFO from overflowing or being emptied in accordance with flow control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.