Limit detector with hysteresis
US7177375B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2003 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Apr 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for processing a signal is presented. An accumulator receives an input signal and generates an accumulated value. A hysteresis controller sets an adjustable upper and lower limit. The upper and lower limits are compared with the accumulated value in a comparator. The comparator outputs a result, which is fed back into the hysteresis controller through a feedback loop. Once the input signal stays within the upper and lower limits, a test signal is considered within specification. When the input signal is outside of the boundary limits, a corrupt test signal is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.