Cache management via statistically adjusted time stamp queue
US7177853B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2002 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Jan 31, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99931
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associate control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.