Method and arrangement for the verification of NV fuses as well as a corresponding computer program product and a corresponding computer-readable storage medium
US7178039B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2002 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Mar 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method and an arrangement for the verification of NV fuses as well as to a corresponding computer program product and to a corresponding computer-readable storage medium which can be used notably for the detection of attacks on the smart card security which modify EEPROM contents and hence also the contents of EEPROM fuses.During the reset phase the fuses are read from the EEPROM. The fuse values successively read out are then automatically verified. One possible implementation is, for example, to load the fuse values read out into a signature register, followed by comparison with a reference value. Appropriate security measures can be activated should the automatic verification indicate an error, for example, due to unauthorized modification of a fuse or attack on the boot operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.