Interconnect circuitry, multichip module, and methods for making them
US7179742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Apr 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of electroless plating metal on a dielectric material includes dipping the dielectric in a solution containing attractive catalytic metal particles and a metal salt solution. A thicker metallic layer can be deposited on top of the resulting layer by electroplating. Electrical circuits and multichip modules including such circuits can be formed having one or more dielectric layers comprised of latex and one or more layers of conductive leads, one or more dielectric layers comprised of a flexible dielectric material, and one or more layers of electrically conductive material patterned to interconnect such ICs. Frames that hold ICs against a substrate may be employed to planarize their top surfaces against the substrate, as well as standard photolithographic techniques in creating conductive paths on the dielectric material between the ICs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.