Tamper barrier for electronic device
US7180008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jun 27, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A tamper protected printed circuit board assembly including a printed circuit board and a partially enveloping tamper wrap covering the entirety of the top surface of the printed circuit board and a first portion of the bottom surface of the printed circuit board, wherein a second portion of the bottom surface of the printed circuit board is not covered by the tamper wrap is provided. The printed circuit board includes two security trace layers each having two security traces thereon, preferably in a serpentine pattern. The tamper wrap and the security traces together cover and prevent tampering with the electronic circuitry of the printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.