Single IC packaging solution for multi chip modules
US7180171B1 · kind B1 · utility
3Cited by
24References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jan 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1572
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multilayer printed circuit board (PCB) interface includes a top PCB layer, a middle PCB layer, and a bottom PCB layer. A top surface of the top PCB layer receives at least one top module. The middle PCB layer includes an electrically conductive layer disposed between two dielectric layers. The electrically conductive layer forms a plurality of connectors protruding horizontally from the sides of the multilayer PCB to couple the PCB interface to a main board. A bottom surface of the bottom PCB layer receives at least one bottom module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.