Variable division method and variable divider
US7180341B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jul 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A feedback path (307) is formed between an output (310c) of a fixed divider (305) and a control terminal (310b) of an inverting/noninverting unit (304). A connection device (306) is arranged on the feedback path (307). The feedback path (307) is connected/disconnected according to the level of the control signal M from outside, thereby switching the number of divisions. The delay time of the signal given to the input terminal (310a) of the inverting/noninverting unit (304) to pass through the feedback path (307) and return to the control terminal (310b) is set greater than the pulse width of the input clock signal. A small pulse input invalidating function is provided in the fixed divider (305). Alternatively, a small pulse output prohibiting function is provided in the inverting/noninverting unit (304). The fixed divider (305) divides the clock signal before division from the inverting/noninverting unit (304) according to the leading edge of the clock pulse of the normal pulse width in the signal (a change point corresponding to the leading edge of the input clock signal).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.