Receiver having full signal path differential offset cancellation capabilities
US7180354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2005 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | May 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.