Semiconductor circuit
US7180356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Mar 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0275
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The level shift circuit in the semiconductor circuit of the invention has a configuration comprising an input stage inverter circuit which inputs an input signal having a first voltage amplitude and outputs an inverted signal of this input signal, an output stage inverter circuit which inputs at least the output signal of the input stage inverter circuit and the output signal has a second voltage amplitude larger than the first voltage amplitude and a bootstrap circuit section which boosts a voltage value of input signal voltage of the output stage inverter circuit and the potential difference of the input signal and the output signal is held as a voltage component. The level shift circuit of each circuit is a Thin-Film Transistor at least using a semiconductor layer composed of amorphous silicon having single channel polarity as a switching element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.