Queue partitioning mechanism
US7180520B2 · kind B2 · utility
0Cited by
5References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Mar 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.