Flexible SDRAM clocking (MS-DLL)
US7180823B1 · kind B1 · utility
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3References
13Claims
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Key dates
| Filing date | Jan 10, 2005 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jan 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay lock loop for use in meeting SDRAM timing requirements, wherein a timing relationship between data generated by a computer chip and a clock in said DRAM is fully programmable, and wherein said delay lock loop is digitally implemented. The delay lock loop includes a first delay chain to measure a number of delay taps in a single clock cycle of the clock of the SDRAM and a second delay chain to delay the clock of the SDRAM. The second delay chain is matched to the first delay chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.