Parallel layer 2 and layer 3 processing components in a network router
US7180893B1 · kind B1 · utility
12Cited by
14References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 22, 2002 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Dec 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When both the L2 and L3 generation units complete their operations for a particular packet, a build component combines the generated L2 and L3 header information from the buffers to form a complete packet header.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.