Backward-compatible parallel DDR bus for use in host-daughtercard interface
US7181551B2 · kind B2 · utility
1Cited by
8References
8Claims
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Key dates
| Filing date | Oct 17, 2003 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Nov 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host-daughtercard interface is pin compatible with a legacy interface but redefines a subset of pins to implement a high-bandwidth double data-rate (DDR) bus. By inspecting a cookie on the daughtercard, the host platform determines whether the daughtercard supports the DDR bus or the legacy interface, and then configures the subset of pins to implement the legacy interface or the DDR bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.