System and method for performing address translation in a computer system
US7181589B2 · kind B2 · utility
4Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jan 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.