Memory address decoding method and related apparatus by bit-pattern matching
US7181591B2 · kind B2 · utility
32Cited by
19References
14Claims
0Family size
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Key dates
| Filing date | Feb 10, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Feb 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address decoding method and related apparatus for deciding which section of a memory device a given address belongs. The memory device has a plurality of sections, each section has a plurality of memory units, and each memory unit has a unique address. The method includes: comparing some specific bits of the given address with predetermined values for deciding which section the given address belongs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.