Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
US7181703B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2003 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jun 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.