Clock delay adjusting method of semiconductor integrated circuit device and semiconductor integrated circuit device formed by the method
US7181709B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Feb 17, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a clock delay adjusting method of a semiconductor integrated circuit device, a plurality of source points for adjusting a clock delay is provided to synchronize a value of the clock delay from each of the source points of each of hierarchical blocks in a semiconductor chip to a clock input circuit operating synchronously with a clock, according to circuit design conditions of the hierarchical blocks. Area terminals are provided in the source points, respectively. A clock input terminal of the semiconductor chip and each area terminal are connected through a clock line so as to be clock distributed over a hierarchical top. A clock delay between the hierarchical blocks is adjusted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.