Composite gate structure in an integrated circuit
US7183596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Jun 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.