Trimmed integrated circuits with fuse circuits
US7183623B2 · kind B2 · utility
2Cited by
19References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2001 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Jan 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer containing integrated circuits having fuses which are selectively blown to trim circuit perimeters. The fuses are located adjacent scribe lanes, and fuse pads are located in the scribe lanes. The integrated circuits are trimmed by selectively energizing the fuse pads to blow selective fuses. When the integrated circuits are severed from the wafer, the fuse pads are severed from the integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.