Configuration memory implementation for LUT-based reconfigurable logic architectures
US7183796B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 2003 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Jun 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, . . . ) for storing settings of the data flow controlling elements (10) and an address decoder (40) for converting an address into selection signals for the memory cells (31a, . . . ). The reconfigurable processing unit of the invention is characterized in that the address decoder (40) is shared between the configuration memory unit (30) and a further memory unit (20), or between two configuration memory units (30, 30′). This provides for a reduction in memory area of the reconfigurable processing unit (1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.