Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme
US7183824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Oct 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided are a duty cycle correction circuit and method for duty cycle correction in a delay locked loop using an inversion locking scheme. The duty cycle correction circuit comprises: a correction unit exchanging and receiving a first duty correction signal and a second duty correction signal and selecting and receiving one of an input clock signal and an inversion signal of the input clock signal in response to an inversion locking signal, and correcting the duty cycle of the received input clock signal or inversion signal of the input clock signal in response to the first and second duty correction signals; a buffer buffering an output signal of the correction unit and outputting the buffered signal as a corrected clock signal; and a duty detector selecting and receiving one of the corrected clock signal and an inversion signal of the corrected clock signal in response to the inversion locking signal, and generating the first and second duty correction signals using the received corrected clock signal or inversion signal of the corrected clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.