Semiconductor memory device
US7184297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Sep 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes: a first node and a second node; a first MIS transistor, having first conductive carrier flows, including a source electrode connected to a first power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; a second MIS transistor, having second conductive carrier flows, including a source electrode connected to a second power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; and a resistance change element connected between the first node and the second node and having a variable resistance due to the direction in which a voltage is applied, wherein information is written in the resistance change element by applying a voltage between the first and the second node, and stored information is read out by applying a low or high input voltage to the first node and reading out a voltage difference in the second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.