Low power programming technique for a floating body memory transistor, memory cell, and memory array
US7184298B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Mar 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.