Semiconductor memory device and control method thereof
US7184322B2 · kind B2 · utility
11Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Nov 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.