Capturing data and crossing clock domains in the absence of a free-running source clock
US7184508B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Apr 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0012
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data, such as data received by a memory I/O from a memory unit in a DDR SDRAM system, is captured using a trigger signal, which may be a non free-running clock signal such as a DQS signal in a DDR SDRAM system, and is transferred to a host system, which may be part of an ASIC, using the host system's clock. The memory I/O includes a data capture register that latches the data received from the memory unit using DQS. The memory I/O also includes a FIFO buffer that latches the data output by the data capture register using a delayed version of DQS. A single edge of the delayed DQS is available to the FIFO for latching each set of data that corresponds to a single pulse of DQS. The FIFO transfers the data to the host system using the host system's clock, which represents a different clock domain than DQS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.