Power conservation system and method
US7184798B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2002 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Mar 3, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A power management circuit is arranged to apply power to and remove power from its own oscillator to conserve power. A power-on reset circuit provides a power-on-reset signal to a state machine. The state machine contains states that are programmed with information that is used to power up or down various subsystems within a device that includes the power management systems, including the oscillator of the state machine. The state machine assumes a known state and applies power to the oscillator in response to the power-on-reset signal. The state machine changes states in response to system events (e.g., a keypress). The state machine also maintains power to the oscillator during the period of time and which the state machine requires clock signal from the oscillator. The state machine can power down the oscillator to conserve power when the state machine does not require a clock signal from the oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.