Lithography method and system with correction of overlay offset errors caused by wafer processing
US7184853B2 · kind B2 · utility
24Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Jun 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic pattern on a wafer layer with a lithographic tool, processing the wafer after the pattern is formed to enable fabrication of a semiconductor device, predicting overlay offset corrections based on one or more factors involved in the processing of the wafer, and utilizing the predicted overlay offset corrections to positionally control the lithographic tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.