Arithmetic structures for programmable logic devices
US7185035B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2003 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Aug 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to some embodiments, arithmetic structures in logic elements result from combining inverters and pass gates (or other multiplexing hardware) with LUT hardware. According to other embodiments, arithmetic structures in logic elements result from combining dedicated adder hardware (e.g., including XOR units) and fracturable LUT hardware. According to other embodiments, arithmetic structures in logic elements result from providing complementary input connections between multiplexers and LUT hardware. In this way, the present invention enables the incorporation of arithmetic structures with LUT structures in a number of ways.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.