System for synchronizing first and second sections of data to opposing polarity edges of a clock
US7185216B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2003 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Nov 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems of and methods for processing data for communication between a sender and a receiver are described. In one embodiment, the phase of a first clock is used to select between first and second portions of data from the sender. The selected data is then synchronized, for communication to the receiver, to a second clock having a frequency which is an integer multiple of that of the first clock, wherein the integer multiple is two or more. The first and second portions of the data may be provided to the same output pins in this embodiment for communication to the receiver. In a second embodiment, first and second portions of data from the sender are clocked in using first and second edges, respectively, of a first clock. The first and second edges have a first polarity if a first pre-determined mode is in effect, and have a second polarity if a second pre-determined mode is in effect. Data derived from the clocked in data is then synchronized, for communication to the receiver, to a second clock. In a third embodiment, data from the sender is clocked in using a first clock. The clocked in data is then transformed responsive to a pre-determined mode selected from a plurality of pos…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.