Processor isolation technique for integrated multi-processor systems
US7185224B1 · kind B1 · utility
10Cited by
86References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 10, 2003 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Apr 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2242
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.