Method and apparatus for implementing a data processor adapted for turbo decoding
US7185260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Mar 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3001
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.