Chip design verifying and chip testing apparatus and method
US7185295B2 · kind B2 · utility
18Cited by
8References
24Claims
0Family size
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Aug 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A chip design verifying and chip testing apparatus is provided including a storing means for storing an application program verifying an operation of a chip and testing the chip, the chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the storing means and the chip, the interface means having a data applying means for applying the I/O file and/or the test vector outputted from the storing means and a data storing means for storing data outputted from the chip; and a computer including a CPU for performing and controlling the application program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.