Semiconductor device with a conductive layer including a copper layer with a dopant
US7187080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Oct 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76888
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.