Semiconductor devices having a pocket line and methods of fabricating the same
US7187082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Apr 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/664
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor device comprises an active region isolated by a device isolation layer placed in a semiconductor substrate having a main surface. A molding hole is placed in the semiconductor substrate on the active region. A pocket insulating layer pattern conformally covers the molding hole. A pocket line extends across the active region, filling the molding hole and protruding from the main surface of the semiconductor substrate. The pocket line includes a pocket conductive layer line, a lower metal layer line, and an upper metal layer line, which are sequentially stacked on the pocket insulating later pattern. The device further may further include a line capping layer pattern placed on the pocket line. The line capping layer pattern and the pocket conductive layer line may surround the lower and upper metal layer lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.