P-domino register
US7187210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2005 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Oct 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.