Yield enhancement of complex chips
US7187383B2 · kind B2 · utility
35Cited by
3References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2002 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Aug 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics processing chip which includes parallel texturing pipelines, with task allocation units which can bypass inoperative ones of said pipelines. Chips which have some but not all pipelines operative can still have full functionality, although performance is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.